1. Field of the Invention
The present invention is related to a nonvolatile semiconductor memory device and in particular is related to a nonvolatile semiconductor memory device which is arranged with a plurality of nonvolatile memory cells and a method of controlling the device.
2. Description of the Related Art
In a nonvolatile semiconductor memory device such as a NAND type flash memory, the interval between adjacent memory cells is becoming narrow due to the progress of miniature processing. Together with a narrowing of the memory cell interval, capacitance between floating gates of adjacent memory cells is becoming larger and the threshold voltage of a memory cell which is programmed first fluctuates depending on the data of an adjacent memory cell which is subsequently programmed.
In addition, together with the progress of miniaturization, the variation in programming characteristics for each cell is increasing. For example, in a memory cell in which the speed at which it reaches a desired data programming state is fast, the possibility of the occurrence of program defect states such as over program (over program state of a selected cell) and program disturb (a state in which a non-selected cell is programmed and the threshold voltage distribution is shifted to a higher region) increases.
In addition, in a nonvolatile semiconductor memory device which includes a memory cell which stores multi-level data of a plurality of bits in one memory cell, many threshold voltage distributions are set and multi-level data is stored compared to a memory cell which stores 2 level data. As a result, it is necessary to very narrowly control the width of one threshold voltage distribution.
A programming method for narrowly controlling the width of a threshold voltage distribution of data to be programmed to a memory cell is disclosed, for example, in a nonvolatile semiconductor memory device cited in Japan Laid Open Patent 2003-196988 and in Japan Laid Open Patent 2004-192789. In the nonvolatile semiconductor memory device cited in Japan Laid Open Patent 2003-196988, the value of a programming control voltage which is supplied to a memory cell is changed according to the programming state of a memory cell and a widening of the threshold voltage distribution is reduced. In addition, in the nonvolatile semiconductor memory device cited in Japan Laid Open Patent 2004-192789, one page of data is programmed to a memory cell while considering the influence of capacitance between floating gates of adjacent memory cells and widening of the threshold voltage distribution is reduced when programming multi-level data.